1. Field of the Invention
This invention generally relates to the fields of semiconductor integrated circuits and electrical interconnect technology, and more particularly relates to vertical or 3D integration of devices such as thin film transistors (TFTs) into back end of the line (BEOL) interconnect structures.
2. Description of the Related Art
In recent years 3D integration has gained significant attention as a possible pathway for increasing IC density and for reducing interconnect delays and ac power consumption (by reducing interconnect distances).
In one prior art technique for fabricating 3D integrated circuits, a process called “smart cut” wafer bonding is used to form a single crystal germanium layer above passivated metal interconnect levels on a silicon device level. This method is described, for example, in Yu. D. S et al, “Three-Dimensional Metal Gate-High-k-GOI CMOSFETs on 1-Poly-6-Metal 0.18-mm Si Devices,” IEEE Electron Device Lett., vol. 26, no. 2, pp. 118-120, February 2005. This method utilizes germanium as an additional device layer stacked over the device layer in the base substrate. Ge offers the advantage of lower temperature processing compared to silicon, a critical factor for vertically integrated device structures that are formed after the first silicon device layer and metal interconnect layers.
However, this method is associated with significant manufacturing problems, which arise from the requirement for wafer bonding above an already-formed interconnect structure. In addition to the cost of wafer bonding, there are concerns with reliability of bonding above the already-formed layers. The cost of losing all of the chips on a 300 mm wafer due to a problem during bonding would be tremendous. Additionally, this type of 3D integration is limited in that it is not easily imbedded in multiple back end of the line (BEOL) wiring levels along with the interconnect structures.
In another prior art 3D vertical integration structure, multiple levels of devices are placed one above the other utilizing single crystal silicon formed by lateral epitaxial growth from a vertical column of silicon seed originating from the Si substrate. This structure is described, for example, in Wei, L. et al. “Vertically Integrated SOI Circuits for Low-Power and High-Performance Applications,” IEEE Transactions on Very Large Scale Integration (VLSI) systems, vol. 10, no. 3, pp. 351-362, June 2002.
This epitaxial growth method of vertical integration has the disadvantage that it is limited to a location close to a seed column.
In addition, Silicon devices require high temperatures for both forming the silicon layer and for later processing steps such as dopant activation. These high temperatures can cause significant degradation to the first device level and prevent the possibility of incorporating these structures in the same level as the back end of the line interconnect levels which are typically limited to a processing temperature of less than 400-450° C.
Therefore, there is a need for a simplified, cost-effective, 3D vertical integration structure and method that could be formed from primarily existing steps and would be compatible with the processing requirements of the BEOL interconnect levels. Implementation of devices into the BEOL wiring levels using primarily standard BEOL processing steps would enable a more cost effective path to 3D integration as compared with the existing prior art.